The Necessary Link between Low-Level and High-Level Synthesis
- Project Title:
- The Necessary Link between Low-Level and High-Level Synthesis
- Work Area:
- Algorithms for Design Methodologies for Complex Circuits & Digital Optical Systems
46, Avenue Felix Viallet
F - 38031 Grenoble Cedex
- Coordinator Country:
- IMEC vzw B
Université Catholique de Louvain B
Universität Dortmund D
Universität Karlsruhe D
Compass Design Automation F
Dassault Electronique F
Technische Universiteit Eindhoven NL
- Contact Point:
- Prof. G. Saucier
- +33/76 574687
- +33/76 503421
- logic synthesis, controller synthesis, architectural synthesis
- Start Date:
- 1 September 92
- 36 months
- This project addresses logic synthesis, focusing on new models as well as a better understanding of the connection to various technological targets, controller synthesis coping with high complexity and using block generators, and architectural design including the use of library blocks and parameterised generators.
This project aims to make significant advances in logic synthesis by exploiting new models such as binary decision diagrams, and to establish a better link with practical issues such as wiring problems and connection to layout generators. It also aims to create a better link with architectural synthesis. For this purpose the logic synthesis methods proposed have to be very robust with respect to complexity and to be able to handle more efficiently the existence of generators and library blocks. Moreover, any restricted technology target, such as a standard cell, is avoided, and new devices, especially CPLDs and FPGAs, widely addressed.
APPROACH AND METHODS
The proposed methods concern three areas:
- Logic synthesis: new models (binary decision diagrams, lexicographical expressions) are investigated and should bring double benefit. They cope better with complexity and take into account wiring and critical path minimisation. Synthesis on FGPAs CPLDs and Standard cells is addresed.
- Controller synthesis: new proposed synthesis methods handle highly complex controllers more efficiently than traditional FSM synthesis tools. They synthesise hierarchical or distributed controllers and use generators such as ROM generators.
- Architectural design: this task, mainly, focuses on a better link between RTL level or high level from VHDL to layout with a special emphasis on the use of parameterised blocks, generators and data path synthesisers.
PROGRESS AND RESULTS
For logic synthesis, the partners appreciate that the state-of-the-art is changing very rapidly due to the extensive use of new representations for Boolean functions, namely the binary decision diagrams. This gives a good chance to new synthesis tools which may provide a significant gain both in results (area/performance) and in running time/memory space. Several partners (INPG, COMPASS, UCL) joined their efforts and significant progress has made in binary decision diagrams construction, input order selection, and in the different use of these representations for synthesis on various targets. Specific mappers on FPGA targets led to immediate technology transfers (INPG) and improvements on standard cells synthesis were pointed out (COMPASS).
For controller synthesis, a dedicated synthesis tool for ultra large Moore controllers described in VHDL and using ROM generators are already available and such a tool is unique. Extension to the use of communicating finite state machines or hierarchical finite state machines is under good progress and both partners (INPG, IMEC) should bring a significant contribution to this strategic topic.
For architectural synthesis, the partners focus on the impact of parametrised generators, on data path synthesisers, on automatic synthesis tools from VHDL (Dortmund, Eindhoven). One of the partners (INPG) is addressing successfully the package partitioning problem and this is of considerable interest.
This project aims to improve the theoretical state-of-the-art of logic synthesis and brings some new highlights to practical issues such as wiring and timing aspects. An important technology transfer effort towards industry is being undertaken by several partners and successful products have emerged. Companies directly involved in the project will benefit from the results, and most academic members are directly engaged in transfers towards industry (IMEC, INPG, Karlsruhe). As an example a start up marketing the results of this projects sells up to 2000 licenses of a synthesis tool in 1992/93.
- Saucier G, Trilhe J Synthesis for Control Dominated Circuits, published by Elsevier, Editors Saucier G, Trilhe J, pp 47-59 (1993)
- Abouzeid P, Babba B, Crastes de Paulet M, Saucier G Input Driven Paritioning Methods and Application to Synthesis on table lookup based FPGAs In: IEE Transactions on CAD (accepted for 1993)
- Saucier G, Fron J, Abouzeid P Lexicographical Expressions of Boolean Functions with Application to Multilevel Synthesis, In: IEEE Transactions on CAD (accepted for 1993)
- Marwedel P Tree-based mapping of algorithms to predefined structures ICCAD 1993
- Saucier G, Brasen D, Hiol J P Partitioning with one structures ICCAD 1993
INFORMATION DISSEMINATION ACTIVITIES
The dissemination of our results has been done through publications, meetings and workshops.
Publications identified in 1993
2 papers IEEE Transactions on CAD
1 paper IEICE Transactions on Information and Systems
1 paper at DAC 93
9 papers at EDAC/Euroasic 93
2 papers at ICCAD 93.
A special workshop, the "International IFIP Workshop on Logic and Architecture Synthesis", was organised to publicise LINK's results.
Invited paper on synthesis by G. Saucier at Journée ARAMIS and EUROPCHIP Australia
Tutorials at EDAC '92, Sasimi '92, EuroASIC '92, DAC '92, EuroASIC '93 and VLSI '93.
Sven Müßig, last update 07-nov-1995. Your feedback is welcome.