Architectural Methodologies for Advanced Testing of VLSI Systems
Description
- Project Title:
- Architectural Methodologies for Advanced Testing of VLSI Systems
- Acronym:
- ARCHIMEDES
- Number:
- 7107
- Work Area:
- Algorithms for design methodologies for complex circuits and digital optical systems
- Coordinator:
- TIMA, Institut National Polytechnique de Grenoble
avenue Felix Viallet 46
F - 38031 GRENOBLE CEDEX
- Coordinator Country:
- F
- Partners
- Universität Hannover, Institut fur Theoretische Elektrotechnik D
Universität Siegen, Fakultat fur Elektrotechnik und Informatik D
Universidad Politecnica de Catalunya, Barcelona E
Universite de Montpelier II-LIRMM F
Universita di Bologna I
INESC, Lisboa P
- Contact Point:
- Dr. B. Courtois
- Telephone:
- +33/76 57 46 15
- Fax:
- +33/76 47 38 14
- E-Mail:
- courtois@archi.imag.fr
- Keywords:
- VLSI systems testing, testable architecture synthesis, IC defects-based testing, BIST
- Start Date:
- 24 July 92
- Duration:
- 36 months
- Status:
- running
- Abstract:
- ARCHIMEDES aims to bridge the gap between two apparently opposing trends in the VLSI design sphere: i) designing circuits from higher and higher levels in order to take advantage of the very large number of devices made available by the progress of technology, ii) efficient testing based on IC defects fault models, which lead to non-affordable times if testing is based on conventional test pattern generation for large designs. To this end, multiple testing methods targeted to multiple types of ICs are being developed using design for testability techniques.
AIMS
ARCHIMEDES aims to answer the following questions:
- how to link architectural design with IC defects-based fault modelling and analysis
- how to merge in a single design the prerequisites for testing off-line (manufacturing) and online testing (lifetime)
- how to take advantage of both voltage testing and current testing
- how to extend to analogue and mixed signal testing what has been done during the last 20 years for digital testing, or what to do if no extension is possible.
No research is expected to be done on existing mature testing techniques. Advances in each area will cross-fertilised in order to obtain a global solution for the architectural synthesis of testable circuits.
APPROACH AND METHODS
Test pattern generation has now attained a good level, and professional CAD software exists to deal with quite large (though limited) parts of designs. Most parts can be dealt with by making them testable at the synthesis stage. To answer the questions raised above, ARCHIMEDES brings together experts on several individual testing methods, approaches and types in order to seek a global solution.
Specific areas of investigation include architectural synthesis, realistic analysis and innovative test techniques.
PROGRESS AND RESULTS
Results have been obtained in many different facets including the following: target structures for datapathes and controllers to be synthesised for off-line testability, regular structures like PLAs designed for on-line testability, the design of optimal analysers and the design of deterministic generators based on LFSROM; emphsis on BiCMOS for defect analysis, on bridging faults for layout design for testability, on analogue and mixed signal for fault modelling; the use of current testing for analogue and mixed-signal circuits, the designs of analogue checkers for on-line testing, the design of built-in current sensors.
POTENTIAL
Research results are expected to contribute to the advance of the state of the art in many facets of testing. Applications are foreseen in industrial advanced products, making a contribution to the three major features governing the success or the failure of an electronic product in the market place: innovation, time-to-market, and quality.
LATEST PUBLICATIONS
- Sebeke C, Ohletz M J Analogue fault simulation Cave Workshop, Dresden, Germany, ( May 1993)
- Dufaza C, Chevalier C, Lew Yan Voon I F C LFSROM: an algorithm for automatic design synthesis of hardware test pattern generator 11th ieee vlsi Test Symposium, Atlantic City, USA, (AprilĘ1993)
- Favalli M, Dalpasso M, Olivo P, Ricco B Analysis of resistive bridging fault detection in BiCMOS digital ICs In: IEEE Trans, on VLSI Systems, to appear
- Simoes M C, Teixeira I M, Teixeira J P Logic circuit extraction for bridging fault equivalence identification in CMOS ICs In: Proc. of European Test Conference (ETC), Rotterdam, The Netherlands (AprilĘ1993)
- Rodriguez-Montannés R, Figueras J, Rubio A Current vs. logic testability of bridges in scan chains In: Proc. of European Test Conference (ETC), Rotterdam, The Netherlands (AprilĘ1993)
- Kolarik V, Lubaszewski M, Courtis B Towards self-checking mixed-signal integrated circuits European Solid-State Circuit Conference, Sevilla, Spain (September 1993)
- Eschermann B Parallel self-test of the JTAG TAP-Controller Journal of Electronic Testing Theory and Applications (jetta), Vol. 4, No. 1 (March 1993)
INFORMATION DISSEMINATION ACTIVITIES
Two open workshops have been organised:
- Mixed-Signal and Analogue Testing, 8-9 June 1993, Hannover
- Synthesis-Architectural Testability Support, 2 July 1993, Montpellier.
Sven Müßig, last update 07-nov-1995. Your feedback is welcome.